Large capacity nonvolatile memory devices which are commonly based on electrically erasable and programmable floating gate memory cells of the FLASH type are used in a number of applications. Typically, these memory devices store a large volume of data that may remain unmodified or may be frequently modified.
In many applications that require a serial access mode for reading stored data, as well as for writing data in a memory array, the first or original factory programming of the memory device is commonly done in a parallel or pseudo-parallel mode. This programming is done by exploiting the “standard” parallel access mode structure of the memory device for speeding up the writing of a large volume of data in the memory before installing the pre-programmed memory device in the intended application system, such as on a PC mother board, for example.
For ordinary operation in the serial mode in many applications, low pin count (LPC) serial communication protocols are privileged. LPC type FLASH memory devices, capable of managing an LPC serial mode and a parallel mode, are thus in demand. These nonvolatile memory devices may require the largest data storage capacity for a certain type of package, and for the size of the device itself. An often required double serial-parallel functioning mode burdens the complexity of the auxiliary circuitry to be integrated in the memory device in addition to the functional circuitry of a standard FLASH memory.